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ZY1207 7A No-Bus POL Data Sheet
3V to 14V Input ? 0.5V to 5.5V Output
4.5
Signal Specifications
Parameter
VDD
Conditions/Description
Internal supply voltage
Min
3.15
Nom
3.3
Max
3.45
Units
V
SYNC Line
ViL_s
ViH_s
Vhyst_s
IoL_s
Ipu_s
Tr_s
Cnode_s
Freq_s
Tsynq
T0
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current V(SYNC)=0.5V
Pull-up current source V(SYNC)=0V
Maximum allowed rise time 10/90%VDD
Added node capacitance
Clock frequency of external SYNC line
Sync pulse duration
Data=0 pulse duration
-0.5
0.75 x
VDD
0.25 x
VDD
14
300
475
22
72
5
0.3 x VDD
VDD + 0.5
0.45 x
VDD
60
1000
300
10
525
28
78
V
V
V
mA
μ A
ns
pF
kHz
% of clock
cycle
% of clock
cycle
Inputs: INTL2…INTL4, CCA0…CCA2, EN, ENP, IM
Iup_x
ViL_x
ViH_x
Vhyst_x
RdnL_x
Pull-up current source V(X)=0
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
External pull down resistance
pin forced low
25
-0.5
0.7 x VDD
0.1 x VDD
110
0.3 x VDD
VDD+0.5
0.3 x VDD
10
μ A
V
V
V
kOhm
Power Good and OK Inputs/Outputs
Iup_PG
Iup_OK
ViL_x
ViH_x
Vhyst_x
IoL_x
Pull-up current source V(PG)=0
Pull-up current source V(OK)=0
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current at 0.5V
25
175
-0.5
0.7 x VDD
0.1 x VDD
4
110
725
0.3 x VDD
VDD+0.5
0.3 x VDD
20
μ A
μ A
V
V
V
mA
Current Share/Sense Bus
Iup_CS
ViL_CS
ViH_CS
Vhyst_CS
IoL_CS
Tr_CS
ZD-00697 Rev. 1.9, 24-Jun-10
Pull-up current source at V(CS)=0V
LOW level input voltage
HIGH level input voltage
Hysteresis of input Schmitt trigger
LOW level sink current V(CS)=0.5V
Maximum allowed rise time 10/90% VDD
www.power-one.com
0.84
-0.5
0.75 x
VDD
0.25 x
VDD
14
3.10
0.3 x VDD
VDD+0.5
0.45 x
VDD
60
100
Page 7 of 18
mA
V
V
V
mA
ns
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